Drawing: |
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Earlier published in: |
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IEC 60617-12 (ed.3.0) 12-39-01 |
Description (temporary field): |
EN |
Single-bit full adder with complementary sum outputs and inverted carry output
(e.g. SN 7480) |
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FR |
Additionneur complet à 1 bit avec des sorties complémentaires pour la somme et une sortie inversée de la retenue
(modèle d'antériorité : SN 7480) |
Name: |
EN |
Single-bit full adder with complementary sum outputs and inverted carry output |
|
FR |
Additionneur complet à 1 bit avec des sorties complémentaires pour la somme et une sortie inversée de la retenue |
Alternative names: |
EN |
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FR |
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Keywords: |
EN |
arithmetic circuits; binary logic circuits |
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FR |
circuits arithmétiques, circuits logiques binaires |
Form: |
EN |
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FR |
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Alternative forms: |
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Applied in: |
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Applies: |
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S01468, S01469, S01497, S01566, S01567, S01643 |
Application notes: |
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A00269 |
Source references: |
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Published in: |
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Entered on: |
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2003-03-18 |
Evaluated on: |
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2004-04-26 |
Released on: |
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2004-09-02 |
Rejected on: |
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Obsolete from: |
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Proposed by: |
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TC3 |
Replaces: |
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Replaced by: |
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Shape class: |
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Characters, Rectangles |
Function class: |
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K Processing signals or information |
Application class: |
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Circuit diagrams |
Symbol restrictions: |
EN |
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FR |
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Remarks: |
EN |
E.g. SN 7480. |
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FR |
Modèle d'antériorité : SN 7480. |
Change requests: |
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C00118, C00189 |